RMQSKA3618DGBA

36-Mbit QDR? II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

Features
PowerSupply 1.8Vforcore(VDD),1.4VtoVDDforI/O(VDDQ)
Clock Fastclockcycletimeforhighbandwidth Twoinputclocks(Kand/K)forpreciseDDRtimingatclockrisingedgesonly Twooutputechoclocks(CQand/CQ)simplifydatacaptureinhigh-speedsystems 

RMQSKA3618DGBA-222#AC0

36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

RMQSKA3618DGBA-222#AC0

36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

RMQSKA3618DGBA-252#AC0

36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

SKU3618

ADAPTADORDEENCAPSULADOTSOP56ADIP56PINES

Descripción EnplasIC&Burn-inSocket,paraencapsulados:TSOP56

TDA3618

Multiplevoltageregulatorwithswitchandignitionbuffers

TDA3618

Multiplevoltageregulatorwithswitchandignitionbuffers

TDA3618AJR

Multiplevoltageregulatorwithswitchandignitionbuffers

TDA3618JR

Multiplevoltageregulatorwithswitchandignitionbuffers

TPS3618

BATTERY-BACKUPSUPERVISORFORRAMRETENTION