RTD2281W中文資料瑞昱數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

General

Embedded 2 DDC with DDC1/2B/CI

Zoom scaling up and down

Embedded one MCU with SPI flash controller.

It contains 4 ADCs in key pad application

Require only one crystal to generate all timing.

Programmable internal low-voltage-reset (LVR)

High resolution 6 channels PWM output, and

wide range selectable PWM frequency.

Support input format up to FHD

Support 27MHz/24MHz/14.318MHz crystal type

Analog RGB Input Interface

1 Analog input supported

Integrated 8-bit triple-channel 210MHz

ADC/PLL

Embedded programmable Schmitt trigger of

HSYNC

Support Sync-On-Green (SOG) and various

kinds of composite sync modes

On-chip high-performance hybrid PLLs

High resolution true 64 phase ADC PLL

YPbPr support up to HDTV 1080p resolution

Digital Input Interface with HDCP

Single link on-chip TMDS receiver support to

165Mhz

Adaptive algorithm for TMDS capability

Data enable only mode support

High-Bandwidth Digital Content Protection

(HDCP 1.3)

Enhanced protection of HDCP secret key

Embedded MCU

Industrial standard 8051 core with external serial

flash

Low speed ADC for various application

I2C Master or Slave hardware supported

Auto Detection /Auto Calibration

Input format detection

Compatibility with standard VESA mode and

support user-defined mode

Smart engine for Phase/Image position/Color

calibration

Scaling

Fully programmable zoom ratios

Independent horizontal/vertical scaling

Advanced zoom algorithm provides high image

quality

Sharpness/Smooth filter enhancement

Support non-linear scaling from 4:3 to 16:9 or

16:9 to 4:3

Color Processor

True 10 bits color processing engine

xvYCC supported

sRGB compliance

Advanced dithering logic for 18-bit panel color

depth enhancement

Dynamic overshoot-smear canceling engine

Brightness and contrast control

Programmable 10-bit gamma support

Peaking/Coring function for video sharpness

VividColor

TM

Independent color management (ICM)

Dynamic contrast control (DCC)

Precise color mapping (PCM)

Output Interface

Fully programmable display timing generator

Flexible data pair swapping for easier system

design.

1 and 2 pixel/clock panel support and up to FHD

resolution. 135MHz for single LVDS. 210MHz

for dual LVDS.

LVDS -output interface on single PCB

Support 8-bit LVDS output

Spread-Spectrum DPLL to reduce EMI

Fixed Last Line output for perfect panel

capability

Embedded OSD

Embedded 20K SRAM dynamically stores OSD

command and fonts

Support multi-color RAM font, 1, 2 and 4-bit per

pixel

64 color palette

Maximum 18 window with alpha-blending/

gradient / gradient target color / gradient reversed

color/ dynamic fade-in/fade-out, bordering/

shadow/3D window type

Rotary 90,180,270 degree

Independent row shadowing/bordering

Programmable blinking effects for each character

OSD-made internal pattern generator for factory

mode

Support 12x18~4x18 proportional font

Hardware decompression for OSD font

Support OSD scrolling

Support 2 independent font based OSD

Power Supply

3.3V / 1.2V power supply

Low standby current (