RZ/N2L中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

200/400 MHz, Arm? Cortex?-R52 on-chip FPU and NEON?, 1.5 MB of on-chip SRAM, Ethernet MAC, EtherCAT, USB 2.0 high-speed, CAN/CANFD, various communications interfaces such as an xSPI and ΔΣ interface, and security functions

Features

■ On-chip 32-bit Arm Cortex-R52 processor

● High-speed realtime control with operating frequency of 200/400

MHz

● On-chip Single 32-bit Arm Cortex-R52 (revision r1p2)

● Tightly coupled memory (TCM) with ECC

– CPU0: 128 KB/128 KB

● Instruction cache/data cache with ECC

– CPU0: 16 KB per cache

● High-speed interrupt

● The FPU supports addition, subtraction, multiplication, division,

multiply-and-accumulate, and square-root operations at singleprecision

and double-precision.

● The NEON, Advanced SIMD, supports integer or single precision

results.

● Harvard architecture with 8-stage pipeline

● Supports the memory protection unit (MPU)

● Arm CoreSight architecture, includes support for debugging

through JTAG and SWD interfaces.