RZ-N2L中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書
| 廠商型號(hào) |
RZ-N2L |
| 功能描述 | RZ Arm-based High-end 32 & 64-bit MPUs |
| 文件大小 |
1.66331 Mbytes |
| 頁面數(shù)量 |
127 頁 |
| 生產(chǎn)廠商 | Renesas Technology Corp |
| 企業(yè)簡稱 |
RENESAS【瑞薩】 |
| 中文名稱 | 瑞薩科技有限公司官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊 | |
| 更新時(shí)間 | 2025-5-15 19:41:00 |
| 人工找貨 | RZ-N2L價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
RZ-N2L規(guī)格書詳情
200/400 MHz, Arm? Cortex?-R52 on-chip FPU and NEON?, 1.5 MB of on-chip SRAM, Ethernet MAC, EtherCAT, USB 2.0 high-speed, CAN/CANFD, various communications interfaces such as an xSPI and ΔΣ interface, and security functions
Features
■ On-chip 32-bit Arm Cortex-R52 processor
● High-speed realtime control with operating frequency of 200/400
MHz
● On-chip Single 32-bit Arm Cortex-R52 (revision r1p2)
● Tightly coupled memory (TCM) with ECC
– CPU0: 128 KB/128 KB
● Instruction cache/data cache with ECC
– CPU0: 16 KB per cache
● High-speed interrupt
● The FPU supports addition, subtraction, multiplication, division,
multiply-and-accumulate, and square-root operations at singleprecision
and double-precision.
● The NEON, Advanced SIMD, supports integer or single precision
results.
● Harvard architecture with 8-stage pipeline
● Supports the memory protection unit (MPU)
● Arm CoreSight architecture, includes support for debugging
through JTAG and SWD interfaces.
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詢價(jià) |
