S26HS01GTGABHV02X中文資料英飛凌數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

? Infineon 45-nm MIRRORBIT? technology that stores two data bits in each memory array cell

? Sector architecture options

- Uniform: Address space consists of all 256KB sectors

- Hybrid

? Configuration 1: Address space consists of thirty-two 4KB sectors grouped either on the top or the bottom

while the remaining sectors are all 256KB

? Configuration 2: Address space consists of thirty-two 4KB sectors equally split between top and bottom

while the remaining sectors are all 256KB

? Page Programming buffer of 256 or 512 bytes

? OTP secure silicon region (SSR) of 1024 bytes (32 × 32 bytes)

? HYPERBUS? interface

- JEDEC eXpanded SPI (JESD251) compatible

- DDR option runs up to 400-MBps (200 MHz clock speed)

- Supports data strobe (DS) to simplify the read data capture in high-speed systems

? Legacy (x1) SPI (1S-1S-1S)

- JEDEC eXpanded SPI (JESD251) compatible

- SDR option runs up to 21-MBps (166 MHz clock speed)

? SEMPER? Flash with HYPERBUS? interface devices support default boot in legacy SPI (x1) or HYPERBUS?

interface (x8)

? Functional safety features

- Functional safety ISO26262 ASIL B compliant and ASIL D ready

- Infineon Endurance Flex architecture provides high-endurance and long retention partitions

- Interface CRC detects errors on communication interface between host controller and SEMPER? Flash device

- Data integrity CRC detects errors in memory array

- SafeBoot reports device initialization failures, detects configuration corruption, and provides recovery

options

- Built-in error correcting code (ECC) corrects Single-bit Error and detects Double-bit Error (SECDED) on memory

array data

- Sector erase status indicator for power loss during erase

? Protection features

- Advanced sector protection for individual memory array sector based protection

? AutoBoot enables immediate access to the memory array following power-on

? Hardware reset through CS# signaling method (JEDEC) AND individual RESET# pin

? Serial flash discoverable parameters (SFDP) describing device functions and features

? Device identification, manufacturer identification and unique identification

? Data integrity

- 256Mb devices

? Minimum 640,000 program-erase cycles for the main array

- 512Mb devices

? Minimum 1,280,000 program-erase cycles for the main array

- 1Gb devices

? Minimum 2,560,000 program-erase cycles for the main array

? All devices

- Minimum 300,000 program-erase cycles for the 4KB sectors

- Minimum 25 years data retention

? Supply voltage

- 1.7V to 2.0V (HS-T)

- 2.7V to 3.6V (HL-T)

? Grade / temperature range

- Industrial (–40°C to +85°C)

- Industrial plus (–40°C to +105°C)

- Automotive AEC-Q100 grade 3 (–40°C to +85°C)

- Automotive AEC-Q100 grade 2 (–40°C to +105°C)

- Automotive AEC-Q100 grade 1 (–40°C to +125°C)

? Packages

- 256Mb and 512Mb: 24-ball BGA 6 × 8 mm

- 1Gb: 24-ball BGA 8 × 8 mm