S27KS0642集成電路（IC）的存儲器規(guī)格書PDF中文資料

Features

Interface

? HyperBus Interface

? 1.8 V / 3.0 V interface support

- Single-ended clock (CK) - 11 bus signals

- Optional differential clock (CK, CK#) - 12 bus signals

? Chip Select (CS#)

? 8-bit data bus (DQ[7:0])

? Hardware reset (RESET#)

? Bidirectional Read-Write Data Strobe (RWDS)

- Output at the start of all transactions to indicate refresh latency

- Output during read transactions as Read Data Strobe

- Input during write transactions as Write Data Mask

? Optional DDR Center-Aligned Read Strobe (DCARS)

- During read transactions RWDS is offset by a second clock, phase shifted from CK

- The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye

Performance, Power, and Packages

? 200 MHz maximum clock rate

? DDR - transfers data on both edges of the clock

? Data throughput up to 400 MBps (3,200 Mbps)

? Configurable Burst Characteristics

- Linear burst

- Wrapped burst lengths:

? 16 bytes (eight clocks)

? 32 bytes (16 clocks)

? 64 bytes (32 clocks)

? 128 bytes (64 clocks)

- Hybrid option - one wrapped burst followed by linear burst

? Configurable output drive strength

? Power Modes

- Hybrid Sleep Mode

- Deep Power Down

? Array Refresh

- Partial Memory Array(1/8, 1/4, 1/2, and so on)

- Full

? Package

- 24-ball FBGA

? Operating Temperature Range

- Automotive, AEC-Q100 Grade 1: –40 °C to +125 °C

Technology

? 38-nm DRAM