S70FL256P集成電路（IC）的存儲器規(guī)格書PDF中文資料

General Description

This document contains information for the S70FL256P device, which is a dual die stack of two S25FL129P die.

Distinctive Characteristics

Architectural Advantages

■ Single power supply operation

– Full voltage range: 2.7 to 3.6V read and write operations

■ Memory architecture

– Uniform 64 kB sectors

– Top or bottom parameter block (Two 64-kB sectors broken down

into sixteen 4-kB sub-sectors each) for each Flash die

– Uniform 256 kB sectors (no 4-kB sub-sectors)

– 256-byte page size

■ Program

– Page Program (up to 256 bytes) in 1.5 ms (typical)

– Program operations are on a page by page basis

– Accelerated programming mode via 9V W#/ACC pin

– Quad Page Programming

■ Erase

– Bulk erase function for each Flash die

– Sector erase (SE) command (D8h) for 64 kB and 256 kB sectors

– Sub-sector erase (P4E) command (20h) for 4 kB sectors

(for uniform 64-kB sector device only)

– Sub-sector erase (P8E) command (40h) for 8 kB sectors

(for uniform 64-kB sector device only)

■ Cycling endurance

– 100,000 cycles per sector typical

■ Data retention

– 20 years typical

■ Device ID

– JEDEC standard two-byte electronic signature

– RES command one-byte electronic signature for backward

compatibility

■ One time programmable (OTP) area on each Flash die for

permanent, secure identification; can be programmed and

locked at the factory or by the customer

■ CFI (Common Flash Interface) compliant: allows host system

to identify and accommodate multiple flash devices

■ Process technology

– Manufactured on 0.09 μm MirrorBit? process technology

■ Package option

– Industry Standard Pinouts

– 16-pin SO package (300 mils)

– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration

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