S70KL1282DPBHV023中文資料英飛凌數(shù)據(jù)手冊PDF規(guī)格書

Features

? Interface

- HYPERBUS? interface

- 1.8 V / 3.0 V interface support

? Single-ended clock (CK) - 11 bus signals

? Optional differential clock (CK, CK#) - 12 bus signals

- Chip select (CS#)

- 8-bit data bus (DQ[7:0])

- Hardware reset (RESET#)

- Bidirectional read-write data strobe (RWDS)

? Output at the start of all transactions to indicate refresh latency

? Output during read transactions as read data strobe

? Input during write transactions as write data mask

- Optional DDR center-aligned read strobe (DCARS)

? During read transactions RWDS is offset by a second clock, phase shifted from CK

? The phase shifted clock is used to move the RWDS transition edge within the read data eye

? Performance, power, and packages

- 200 MHz maximum clock rate

- DDR - transfers data on both edges of the clock

- Data throughput up to 400 MBps (3,200 Mbps)

- Configurable burst characteristics

? Linear burst

? Wrapped burst lengths:

16 bytes (8 clocks)

32 bytes (16 clocks)

64 bytes (32 clocks)

128 bytes (64 clocks)

? Hybrid option - one wrapped burst followed by linear burst on 64 Mb. Linear burst across die boundary is

not supported.

- Configurable output drive strength

- Power modes[1]

? Hybrid sleep mode

? Deep power down

- Array refresh

? Partial memory array(1/8, 1/4, 1/2, and so on)

? Full memory array

- Package

? 24-ball FBGA

- Operating temperature range

? Industrial (I): –40°C to +85°C

? Industrial plus (V): –40°C to +105°C

? Automotive (A), AEC-Q100 grade 3: –40°C to +85°C

? Automotive (B), AEC-Q100 grade 2: –40°C to +105°C

? Technology

- 38-nm DRAM