SAB-R3020-25-N中文資料西門子數(shù)據(jù)手冊PDF規(guī)格書

Introduction

The SAB-R3020/SAB-R2020 write buffer enhances performance of MIPS architecture based systems by allowing the processor to perform write operations during rn cycles instead of stalling the pipeline. Each device handles an 8-bit slice of address and a 9-bit slice of data (one parity bit per byte). Four wirte buffers are used per system to provide four-deep buffering of 32 bits of address and 36 bits of data and parity.