SH7203中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

SH7203 Features

This LSI is a single-chip RISC (reduced instruction set computer) microcontroller that includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system.

The CPU in this LSI is the SH-2A CPU that provides upward compatibility for SH-1, SH-2, and SH-2E CPUs at object code level. It has a RISC-type instruction set and uses a superscalar architecture and a Harvard architecture, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture that is independent from the direct memory access controller (DMAC) enhances data processing power. This CPU brings the user the ability to set up high-performance systems with strong functionality at less expense than was achievable with previous microcontrollers, and is even able to handle realtime control applications requiring highspeed characteristics.