SI5310-GM集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Description

The Si5310 is a fully integrated low-power clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. The clock regenerator operates simultaneously, creating a “clean” version of the input clock by using the clock synthesis phase-locked loop (PLL) to remove unwanted jitter and square up the input clock’s rising and falling edges. The Si5310 uses Silicon Laboratories patented DSPLL? architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs with a digital signal-processing algorithm.

Features

Complete precision clock multiplier and clock regenerator device:

■ Performs clock multiplication to one of two frequency ranges: 150–167 MHz or 600–668 MHz

■ Jitter generation as low as 0.5 psrms for 622 MHz output

■ Accepts input clock from 9.4–668 MHz

■ Regenerates a “clean”, jitterattenuated version of input clock

■ DSPLL? technology provides superior jitter performance

■ Small footprint: 4 x 4 mm

■ Low power: 310 mW typical

■ ROHS-compliant Pb-free packaging option available

Applications

■ SONET/SDH systems

■ Terabit routers

■ Digital cross connects

■ Optical transceiver modules

■ Gigabit Ethernet systems

■ Fibre channel