Features

? Supports single-ended or

differential input clock signals

? Generates four differential

(LVPECL, LVDS, HCSL) or eight

single-ended (CMOS, SSTL,

HSTL) outputs

? Provides signal level translation

??Differential to single-ended

??Single-ended to differential

??Differential to differential

??Single-ended to single-ended

? Wide frequency range

??LVPECL, LVDS: 5 to 710 MHz

??HCSL: 5 to 250 MHz

??SSTL, HSTL: 5 to 350 MHz

??CMOS: 5 to 200 MHz

? Additive jitter: 150 fs RMS typ

? Output-output skew: 100 ps

? Propagation delay: 2.5 ns typ

? Single core supply with excellent

PSRR: 1.8, 2.5, or 3.3 V

? Output driver supply voltage

independent of core supply: 1.5,

1.8, 2.5, or 3.3 V

? Loss of Signal (LOS) indicator

allows system clock monitoring

? Output Enable (OEB) pin allows

glitchless control of output clocks

? Low power: 10 mA typical core

current

? Industrial temperature range:

–40 to +85 °C

? Small size: 24-lead, 4 x 4 mm

QFN

SI5330屬于集成電路（IC） > 時(shí)鐘緩沖器，驅(qū)動(dòng)器。美國思佳訊公司制造生產(chǎn)的SI5330時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個(gè)整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。