Si5365集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Description

The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 710 MHz and generates two low jitter clock outputs at the same frequency. The clock frequency range and loop bandwidth are selectable from a simple look-up table. The Si5317 is based on Silicon Laboratories 3rd-generation DSPLL? technology, which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user selectable, providing jitter performance optimization at the application level.

Features

■ Provides jitter attenuation on any frequency

■ One clock input / two clock outputs

■ Input/output frequency range: 1–710 MHz

■ Ultra low jitter: 300 fs (12 kHz–20 MHz) typical

■ Simple pin control interface

■ Selectable loop bandwidth for jitter attenuation: 60 Hz–8.4 kHz

■ Selectable output clock signal format: LVPECL, LVDS, CML or CMOS

■ Single supply: 1.8, 2.5, or 3.3 V

■ VCO freeze during LOS/LOL

■ Loss of lock and loss of signal alarms

■ On-chip voltage regulator with high PSRR

■ Small size: 6 x 6 mm, 36-QFN

■ Wide temperature range: –40 to +85 oC

Applications

■ Data converter clocking

■ Wireless infrastructure

■ Networking, SONET/SDH

■ Switches and routers

■ Medical instrumentation

■ Test and measurement