SI5376-EVB開(kāi)發(fā)板套件編程器的評(píng)估演示板及套件規(guī)格書(shū)PDF中文資料

SI5376-EVB屬于開(kāi)發(fā)板套件編程器的評(píng)估演示板及套件。由美國(guó)思佳訊公司制造生產(chǎn)的SI5376-EVB評(píng)估和演示板及套件該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過(guò)驗(yàn)證的實(shí)施環(huán)境中評(píng)估某些重點(diǎn)器件的性能或特性。評(píng)估方法通常有完善的文檔說(shuō)明，并且視乎具體情況由評(píng)估軟件提供支持。產(chǎn)品通常由印刷電路板組成，板上已裝有重點(diǎn)器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對(duì)于數(shù)量特別多或類(lèi)別獨(dú)特的器件類(lèi)別(如 ADC、DAC 和開(kāi)關(guān)模式電源)，評(píng)估平臺(tái)可組合為一個(gè)單獨(dú)的產(chǎn)品系列。

Features

? Highly-integrated, 4 PLL clock

multiplier/jitter attenuator

? Four independent DSPLLs support

any-frequency synthesis and jitter

attenuation

? 8 inputs/8 outputs

? Each DSPLL can generate any

frequency from 2 kHz to 808 MHz

from a 2 kHz to 710 MHz input

? 350 fs rms (12 kHz– 20 MHz) and

410 fs rms (50 kHz–80 MHz)

typical

? Meets ITU-T G.8251 and Telcordia

GR-253-CORE OC-192 jitter

specifications

? Programmable loop bandwidth:

60 Hz to 8 kHz

? Faster lock acquisition compared to

the Si5374: <1.2 s

? For a very low-loop BW version, see

the Si5374

? Supports all ITU G.709 and any

custom FEC ratios (239/237,

255/238, 255/237, 255/236, 253/226)

? Integrated loop filter with

programmable bandwidth

? Simultaneous free-run and

synchronous operation

? Automatic/manual hitless input clock

switching

? Selectable output clock signal format

(LVPECL, LVDS, CML, CMOS)

? LOL and interrupt alarm outputs

? I2C programmable

? Single 1.8 V ±5 or 2.5 V ±10

operation with high PSRR on-chip

voltage regulator

? 10x10 mm PBGA