SJA1124_V01中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

description

The SJA1124 is a quad Local Interconnect Network (LIN) commander channel device.

Each of the four channels contains a LIN commander controller and LIN transceiver with

commander termination. LIN commander frames are transferred to the physical LIN bus

via the LIN physical layer. The SJA1124 is primarily intended for in-vehicle subnetworks

using baud rates up to 20 kBd and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A,

ISO 17987-4:2016 (12 V LIN) and SAE J2602-1. It is available in two variants, SJA1124A

and SJA1124B; see Section 3 for details.

A Serial Peripheral Interface (SPI) and an interrupt output provide the interface between

the SJA1124 and a microcontroller.

Transmit data streams received on the SPI are converted by the SJA1124 into LIN

commander frames transmitted on the LIN bus. The LIN commander frames are

transmitted as optimized bus signals shaped to minimize ElectroMagnetic Emission

(EME). The LIN bus output pins are pulled HIGH via internal LIN commander termination

resistors. Data streams received on the LIN bus input pins can be read by the

microcontroller via the SPI.

Power consumption is very low in Low Power mode. However, the SJA1124 can still be

woken up via the LIN pins and the SPI interface.

Features

2.1 General

? Four LIN commander channels:

– LIN commander controller

– LIN transceiver

– LIN commander termination consisting of a diode and a pull-up resistor

? Compliant with:

– LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A

– ISO 17987-3:2016, ISO 17987-4:2016 (12 V LIN)

– SAE J2602-1

? Very low current consumption in Low Power mode with wake-up via SPI or LIN

? Option to control an external voltage regulator via the INHN output

? Bus signal shaping optimized for baud rates up to 20 kBd

? SPI for communicating with the microcontroller:

– SPI used for configuration, control, diagnosis and LIN data transfer

– Flexible SPI length from 3 bytes to 18 bytes

– Output status pin signals SPI operational state

? Interrupt output pin: interrupts can be configured individually

? Facilitates synchronous LIN frame transmission across multiple SJA1124 devices

? VIO input for direct interfacing with 3.3 V and 5 V microcontrollers

? On-chip Phase-Locked Loop (PLL) for LIN commander controller

? Passive behavior in unpowered state

? Undervoltage detection

? Leadless DHVQFN24 package (3.5 mm × 5.5 mm) supporting improved Automated

Optical Inspection (AOI) capability

2.2 LIN commander controllers

? Independent per LIN channel:

– Baud rate

– Operating mode

– Status and interrupt

? Complete LIN frame handling and transfer

? One interrupt per LIN frame

? Slave response timeout detection

? Programmable break length

? Automatic sync field generation

? Programmable stop bit length

? Hardware parity generation

? Hardware or software checksum generation

? Fault confinement

? Fractional baud rate generator

2.3 Protection

? Excellent ElectroMagnetic Immunity (EMI)

? Very high ESD robustness: ±6 kV according to IEC61000-4-2 for pins LIN1 to LIN4 and

BAT

? Bus terminal and battery pin protected against transients in the automotive environment

(ISO 7637)

? Bus terminal short-circuit proof to battery and ground

? LIN dominant timeout function

? Thermal protection