SL2305SI-1集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書(shū)PDF中文資料

Description

The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin.

Key Features

? 10 to 140 MHz operating frequency range

? Low output clock jitter:

- 140 ps-max c-c-j at 66 MHz

? Low output-to-output skew: 150 ps-max

? Low product-to-product skew: 400 ps-max

? 3.3 V power supply range

? Low power dissipation:

- 14 mA-max at 66MHz

- 26 mA-max at 133 MHz

? One input drives 5 outputs organized as 4+1

? SpreadThru? PLL that allows use of SSCG

? Standard and High-Drive options

? Available in 8-pin SOIC and TSSOP packages

? Available in Commercial and Industrial grades

Applications

? Printers and MFPs

? Digital Copiers

? PCs and Work Stations

? DTV

? Routers, Switchers and Servers

? Digital Embeded Systems