SL23EP08集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Description

The SL23EP08 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications.

Key Features

? 10 to 220 MHz operating frequency range

? Low output clock skew: 45ps-typ

? Low output clock jitter:

- 25 ps-typ cycle-to-cycle jitter

- 15 ps-typ period jitter

? Low part-to-part output skew: 90 ps-typ

? Wide 2.5 V to 3.3 V power supply range

? Low power dissipation:

- 20 mA-max at 66 MHz and VDD=3.3 V

- 18 mA-max at 66 MHz and VDD=2.5V

? One input drives 8 outputs

? Multiple configurations and drive options

? Select mode to bypass PLL or tri-state outputs

? SpreadThru? PLL that allows use of SSCG

? Available in 16-pin SOIC and TSSOP packages

? Available in Commercial and Industrial grades

Benefits

? Up to eight (8) distribution of input clock

? Standard and High-Dirive levels to control impedance level, frequency range and EMI

? Low power dissipation, jitter and skew

? Low cost

Applications

? Printers, MFPs and Digital Copiers

? PCs and Work Stations

? Routers, Switchers and Servers

? Datacom and Telecom

? High-SpeedDigital Embeded Systems