SL4052BN中文資料SLS數(shù)據(jù)手冊(cè)PDF規(guī)格書
廠商型號(hào) |
SL4052BN |
功能描述 | Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS |
文件大小 |
61.29 Kbytes |
頁(yè)面數(shù)量 |
6 頁(yè) |
生產(chǎn)廠商 | System Logic Semiconductor |
企業(yè)簡(jiǎn)稱 |
SLS |
中文名稱 | System Logic Semiconductor官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-1-8 18:30:00 |
SL4052BN規(guī)格書詳情
Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS
The SL4052B analog multiplexer/demultiplexer is digitally controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V peak-to-peak can be achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V, a VCC - VEE of up to 13 V can be controlled; for VCC - VEE level differences above 13V a VCC - GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power over the full VCC -GND and VCC - VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1”is present at the ENABLE input terminal all channels are off.
The SL4052 is a differential 4-channel multiplexer having two binary control inputs. A and B, and an enable input. The two binary input signals select 1 of 4 pairs of channels to turned on and connect the analog inputs to the outputs.
? Operating Voltage Range: 3.0 to 18 V
? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
? Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
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