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SL74LS138N中文資料SLS數(shù)據(jù)手冊PDF規(guī)格書
| 廠商型號 |
SL74LS138N |
| 功能描述 | 3-to-8-Line Decoder/Demultiplexer |
| 文件大小 |
33.01 Kbytes |
| 頁面數(shù)量 |
3 頁 |
| 生產(chǎn)廠商 | System Logic Semiconductor |
| 企業(yè)簡稱 |
SLS |
| 中文名稱 | System Logic Semiconductor官網(wǎng) |
| 原廠標(biāo)識 |  |
| 數(shù)據(jù)手冊 | |
| 更新時(shí)間 | 2025-3-11 18:22:00 |
| 人工找貨 | SL74LS138N價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
SL74LS138N規(guī)格書詳情
This schottky-clamped TTL MSI circuit is designed to be used in high-performance memory-decording or data-routing applications requiring very short propagation delay time. In high-performance memory systems this decode can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit the delay times of this decorder and the enable time of the memory are usually less than the typical access times of the memory. This means that the effective system delay introduced by the schottky-clampled system decoder is negligible.
· Designed Specifically for High Speed Memory Decoders and Data Transmission Systems
· Incorporate 3 Enabler Inputs to Simplify Cascading AND/OR Data Reception
· Schottky Clamped for High Performance
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Slkor(薩科微) |
2021+ |
SOT-89 |
1394 |
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TI |
23+ |
NA |
1335 |
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SLS |
24+ |
NA |
990000 |
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SONNENSCH |
23+ |
11200 |
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24+ |
SOP-7.2-20P |
4897 |
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詢價(jià) | ||
ST |
23+ |
DIP-24 |
16900 |
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詢價(jià) | ||
SLKOR(薩科微) |
24+ |
* |
10 |
C06-二極管 |
詢價(jià) | ||
24+ |
SOP-20P |
85 |
詢價(jià) | ||||
SLS |
22+ |
SOP |
12000 |
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詢價(jià) | ||
SLKOR(薩科微) |
24+ |
con |
10000 |
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詢價(jià) |
