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SN54-74LS390中文資料安森美半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
SN54-74LS390規(guī)格書(shū)詳情
The SN54/74LS390 and SN54/74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input for each section. The two sections can be connected to count in the 8.4.2.1 BCD code or they can count in a biquinary sequence to provide a square wave (50 duty cycle) at the final output.
Each half of the LS393 operates as a Modulo-16 binary divider, with the last three stages triggered in a ripple fashion. In both the LS390 and the LS393, the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs.
Each half of each circuit type has a Master Reset input which responds to a HIGH signal by forcing all four outputs to the LOW state.
? Dual Versions of LS290 and LS293
? LS390 has Separate Clocks Allowing ÷2, ÷2.5, ÷5
? Individual Asynchronous Clear for Each Counter
? Typical Max Count Frequency of 50 MHz
? Input Clamp Diodes Minimize High Speed Termination Effects
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---|---|---|---|---|---|---|---|
TI(德州儀器) |
23+ |
NA/ |
7350 |
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23+ |
NA/ |
24 |
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詢價(jià) | ||
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2020+ |
CDIP |
80000 |
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TI |
24+ |
35200 |
一級(jí)代理/放心采購(gòu) |
詢價(jià) | |||
原廠 |
NA |
8650 |
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詢價(jià) | |||
TI/德州儀器 |
22+ |
CDIP |
12245 |
現(xiàn)貨,原廠原裝假一罰十! |
詢價(jià) | ||
TI |
23+ |
CDIP |
3200 |
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TI/德州儀器 |
22+ |
2450 |
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TI |
2016+ |
DIP |
6528 |
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CDIP |
899933 |
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