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SN54AHC74_V01中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠(chǎng)商型號(hào) |
SN54AHC74_V01 |
功能描述 | SNx4AHC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset |
文件大小 |
3.27085 Mbytes |
頁(yè)面數(shù)量 |
42 頁(yè) |
生產(chǎn)廠(chǎng)商 | Texas Instruments |
企業(yè)簡(jiǎn)稱(chēng) |
TI【德州儀器】 |
中文名稱(chēng) | 美國(guó)德州儀器公司官網(wǎng) |
原廠(chǎng)標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-1-26 16:00:00 |
SN54AHC74_V01規(guī)格書(shū)詳情
1 Features
? Operating range 2-V to 5.5-V VCC
? Latch-up performance exceeds 250 mA per JESD
17
? ESD protection exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
? Convert a momentary switch to a toggle switch
? Hold a signal during controller reset
? Input slow edge-rate signals
? Operate in noisy environments
? Divide a clock signal by two
3 Description
The SNx4AHC74 dual positive-edge-triggered devices
are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on
the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
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20 |
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