首頁>SN54SC4T02-SEP>規(guī)格書詳情

SN54SC4T02-SEP中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

SN54SC4T02-SEP
廠商型號

SN54SC4T02-SEP

功能描述

SN54SC4T02-SEP Radiation Tolerant, Quadruple 2-Input Positive-NOR Gates

文件大小

946.29 Kbytes

頁面數(shù)量

20

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI德州儀器

中文名稱

美國德州儀器公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2024-12-29 16:00:00

SN54SC4T02-SEP規(guī)格書詳情

1 Features

? Vendor item drawing available, VID

V62/23628-01XE

? Total ionizing dose characterized at 30 krad (Si)

– Total ionizing dose radiation lot acceptance

testing (TID RLAT) for every wafer lot to 30

krad (Si)

? Single-event effects (SEE) characterized:

– Single event latch-up (SEL) immune to linear

energy transfer (LET) = 43 MeV-cm2 /mg

– Single event transient (SET) characterized to

43 MeV-cm2 /mg

? Wide operating range of 1.2 V to 5.5 V

? Single-supply translating gates at 5/3.3/2.5/1.8/1.2

V VCC

– TTL compatible inputs:

? Up translation:

– 1.8-V – Inputs from 1.2 V

– 2.5-V – Inputs from 1.8 V

– 3.3-V – Inputs from 1.8 V, 2.5 V

– 5.0-V – Inputs from 2.5 V, 3.3 V

? Down translation:

– 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V,

5.0 V

– 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V

– 2.5-V – Inputs from 3.3 V, 5.0 V

– 3.3-V – Inputs from 5.0 V

? 5.5 V tolerant input pins

? Output drive up to 25 mA AT 5-V

? Latch-up performance exceeds 250 mA per

JESD 17

? Space enhanced plastic (SEP)

– Controlled baseline

– Gold bondwire

– NiPdAu lead finish

– One assembly and test site

– One fabrication site

– Military (–55°C to 125°C) temperature range

– Extended product life cycle

– Product traceability

– Meets NASAs ASTM E595 outgassing

specification

2 Applications

? Enable or disable a digital signal

? Controlling an indicator LED

? Translation between communication modules and

system controllers

3 Description

The SN54SC4T02-SEP contains four independent 2-

input NOR Gates with extended voltage operation

to allow for level translation. Each gate performs

the Boolean function Y = A + B in positive logic.

The output level is referenced to the supply voltage

(VCC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V

CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example 1.2 V input to 1.8 V output or 1.8 V input

to 3.3 V output). Additionally, the 5-V tolerant input

pins enable down translation (for example 3.3 V to 2.5

V output).

供應商 型號 品牌 批號 封裝 庫存 備注 價格
24+
3000
自己現(xiàn)貨
詢價
TI/德州儀器
2122+
CDIP
11190
全新原裝正品現(xiàn)貨,優(yōu)勢渠道可含稅,假一賠十
詢價
TI
23+
CDIP
5000
原裝正品,假一罰十
詢價
TI
2020+
DIP
80000
只做自己庫存,全新原裝進口正品假一賠百,可開13%增
詢價
TI/德州儀器
22+
CDIP
11190
原裝正品
詢價
TI
18+
CDIP
85600
保證進口原裝可開17%增值稅發(fā)票
詢價
TI/BB
24+
原廠原裝
19800
絕對原裝進口現(xiàn)貨,假一賠十,價格優(yōu)勢!
詢價
最新
2000
原裝正品現(xiàn)貨
詢價
TI
22+
NA
500000
萬三科技,秉承原裝,購芯無憂
詢價
Texas Instruments
2022+
原廠原包裝
8600
全新原裝 支持表配單 中國著名電子元器件獨立分銷
詢價