SN74AHC74QPWRG4Q1集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

SN74AHC74QPWRG4Q1屬于集成電路（IC）的觸發(fā)器。由德州儀器制造生產(chǎn)的SN74AHC74QPWRG4Q1觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。

1 Features

? AEC-Q100 qualified for automotive applications:

– Device temperature grade 1: -40°C to +125°C

– Device HBM ESD classification level 2

– Device CDM ESD classification level C4B

? Available in wettable flank QFN package

? Operating range 2-V to 5.5-V VCC

? Latch-up performance exceeds 250 mA

per JESD 17

2 Applications

? Convert a momentary switch to a toggle switch

? Hold a signal during controller reset

? Divide a clock signal by two

3 Description

The SN74AHC74Q-Q1 dual positive-edge-triggered

device is a D-type flip-flop.

A low level at the preset (PRE) or clear (CLR) inputs

sets or resets the outputs, regardless of the levels

of the other inputs. When PRE and CLR are inactive

(high), data at the data (D) input meeting the setup

time requirements is transferred to the outputs on

the positive-going edge of the clock pulse. Clock

triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following

the hold-time interval, data at the D input can be

changed without affecting the levels at the outputs.