SN74AHCT138QDRQ1集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

SN74AHCT138QDRQ1屬于集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器。由德州儀器制造生產(chǎn)的SN74AHCT138QDRQ1信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器邏輯型信號(hào)開(kāi)關(guān)、多路復(fù)用器和編碼器 IC 可用于對(duì)以數(shù)字格式表示數(shù)據(jù)的電信號(hào)進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號(hào)的類似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無(wú)窮變化量。

1 Features

? Qualified for Automotive Applications

? EPIC (Enhanced-Performance Implanted CMOS)

Process

? Inputs Are TTL-Voltage Compatible

? Designed Specifically for High-Speed Memory

Decoders and Data-Transmission Systems

? Incorporates Three Enable Inputs to Simplify

Cascading and/or Data Reception

? Latch-Up Performance Exceeds 250mA Per JESD

17

? ESD Protection Exceeds 2000V Per MIL-STD-833,

Method 3015

2 Description

The SN74AHCT138Q 3-line to 8-line decoder/

demultiplexer is designed to be used in highperformance

memory-decoding and data-routing

applications that require very short propagation-delay

times. In high-performance memory systems, this

decoder can be used to minimize the effects of

system decoding. When employed with high-speed

memories utilizing a fast enable circuit, the delay

times of this decoder and the enable time of the

memory usually are less than the typical access time

of the memory. This means that the effective system

delay introduced by the decoder is negligible.