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SN74LV2T74-Q1中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
SN74LV2T74-Q1 |
功能描述 | SN74LV2T74-EP Enhanced Product, Dual D-Type Flip-Flop With Integrated Translation |
文件大小 |
1.05054 Mbytes |
頁(yè)面數(shù)量 |
25 頁(yè) |
生產(chǎn)廠商 | Texas Instruments |
企業(yè)簡(jiǎn)稱 |
TI1【德州儀器】 |
中文名稱 | 德州儀器官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-1-27 22:30:00 |
SN74LV2T74-Q1規(guī)格書(shū)詳情
1 Features
? Wide operating range of 1.8 V to 5.5 V
? Single-supply voltage translator (refer to LVxT
Enhanced Input Voltage):
– Up translation:
? 1.2 V to 1.8 V
? 1.5 V to 2.5 V
? 1.8 V to 3.3 V
? 3.3 V to 5.0 V
– Down translation:
? 5.0 V, 3.3 V, 2.5 V to 1.8 V
? 5.0 V, 3.3 V to 2.5 V
? 5.0 V to 3.3 V
? 5.5-V tolerant input pins
? Supports standard pinouts
? Up to 150 Mbps with 5-V or 3.3-V VCC
? Latch-up performance exceeds 250 mA
per JESD 17
? Supports defense, aerospace, and medical
applications:
– Controlled baseline
– One assembly and test site
– One fabrication site
– Extended product life cycle
– Product traceability
2 Applications
? Convert a momentary switch to a toggle switch
? Hold a signal during controller reset
? Input slow edge-rate signals
? Operate in noisy environments
? Divide a clock signal by two
3 Description
The SN74LV2T74-EP contains two independent Dtype
positive-edge-triggered flip-flops. A low level at
the preset (PRE) input sets the output high. A low
level at the clear (CLR) input resets the output low.
Preset and clear functions are asynchronous and not
dependent on the levels of the other inputs. When
PRE and CLR are inactive (high), data at the data
(D) input meeting the setup time requirements is
transferred to the outputs (Q, Q) on the positive-going
edge of the clock (CLK) pulse. Clock triggering occurs
at a voltage level and is not directly related to the
rise time of the input clock (CLK) signal. Following
the hold-time interval, data at the data (D) input can
be changed without affecting the levels at the outputs
(Q, Q). The output level is referenced to the supply
voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and
5-V CMOS levels.
The input is designed with a lower threshold circuit to
support up translation for lower voltage CMOS inputs
(for example, 1.2 V input to 1.8 V output or 1.8 V input
to 3.3 V output). In addition, the 5-V tolerant input pins
enable down translation (for example, 3.3 V to 2.5 V
output).
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
TI |
2020+ |
SOIC-14 |
80000 |
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增 |
詢價(jià) | ||
TEXAS |
TSSOP14L |
893993 |
集團(tuán)化配單-有更多數(shù)量-免費(fèi)送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢價(jià) | |||
24+ |
SSOP |
500 |
本站現(xiàn)庫(kù)存 |
詢價(jià) | |||
TexasInstruments |
18+ |
ICQUAD2-INPUTORGATE14-SO |
6800 |
公司原裝現(xiàn)貨/歡迎來(lái)電咨詢! |
詢價(jià) | ||
TI |
23+ |
N/A |
8000 |
只做原裝現(xiàn)貨 |
詢價(jià) | ||
TI |
23+ |
N/A |
7000 |
詢價(jià) | |||
TI/德州儀器 |
22+ |
TSSOP |
20000 |
原裝現(xiàn)貨,實(shí)單支持 |
詢價(jià) | ||
TI/德州儀器 |
2021+ |
TSSOP14 |
100500 |
一級(jí)代理專營(yíng)品牌!原裝正品,優(yōu)勢(shì)現(xiàn)貨,長(zhǎng)期排單到貨 |
詢價(jià) | ||
TI德州儀器 |
22+ |
24000 |
原裝正品現(xiàn)貨,實(shí)單可談,量大價(jià)優(yōu) |
詢價(jià) | |||
1000 |
原裝正品 |
詢價(jià) |