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SN74LV4T125-EP中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

SN74LV4T125-EP
廠商型號(hào)

SN74LV4T125-EP

功能描述

SN74LV4T125-EP Single Power Supply Quadruple Buffer Translator GATE With 3- State Output CMOS Logic Level Shifter

文件大小

1.05524 Mbytes

頁面數(shù)量

23

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI1德州儀器

中文名稱

德州儀器官網(wǎng)

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數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-1-15 14:34:00

SN74LV4T125-EP規(guī)格書詳情

1 Features

? Wide operating range of 1.8V to 5.5V

? Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

? 1.2V to 1.8V

? 1.5V to 2.5V

? 1.8V to 3.3V

? 3.3V to 5.0V

– Down translation:

? 5.0V, 3.3V, 2.5V to 1.8V

? 5.0V, 3.3V to 2.5V

? 5.0V to 3.3V

? 5.5V tolerant input pins

? Supports standard pinouts

? Up to 150Mbps with 5V or 3.3V VCC

? Latch-up performance exceeds 250mA per JESD

17

2 Applications

? Enable or disable a digital signal

? Controlling an indicator LED

? Translation between communication modules and

system controllers

3 Description

The SN74LV4T125-EP contains four independent

buffers with 3-state outputs and extended voltage

operation to allow for level translation. Each buffer

performs the Boolean function Y = A in positive logic.

The outputs can be put into a high impedance (Hi-Z)

state by applying a HIGH on the OE pin. The output

level is referenced to the supply voltage (VCC) and

supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2V input to 1.8V output or 1.8V input

to 3.3V output). In addition, the 5V tolerant input pins

enable down translation (for example, 3.3V to 2.5V

output).

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
TI(德州儀器)
23+
NA
20094
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TI/德州儀器
22+
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6000
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TI/德州儀器
23+
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10000
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TI(德州儀器)
10000
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TI/德州儀器
23+
TSSOP14
8678
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TI
21+
TSSOP14
10000
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TI/德州儀器
2023+
TSSOP14
15861
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TI
2020+
TSSOP
80000
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TI
20+
TSSOP
19570
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TI(德州儀器)
22+
NA
6000
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