SN74LV4T125集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書(shū)PDF中文資料

SN74LV4T125屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由德州儀器制造生產(chǎn)的SN74LV4T125緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪(fǎng)問(wèn)，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線(xiàn)之間進(jìn)行隔離通信。

1 Features

? Wide operating range of 1.8V to 5.5V

? Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

? 1.2V to 1.8V

? 1.5V to 2.5V

? 1.8V to 3.3V

? 3.3V to 5.0V

– Down translation:

? 5.0V, 3.3V, 2.5V to 1.8V

? 5.0V, 3.3V to 2.5V

? 5.0V to 3.3V

? 5.5V tolerant input pins

? Supports standard pinouts

? Up to 150Mbps with 5V or 3.3V VCC

? Latch-up performance exceeds 250mA per JESD

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2 Applications

? Enable or disable a digital signal

? Controlling an indicator LED

? Translation between communication modules and

system controllers

3 Description

The SN74LV4T125-EP contains four independent

buffers with 3-state outputs and extended voltage

operation to allow for level translation. Each buffer

performs the Boolean function Y = A in positive logic.

The outputs can be put into a high impedance (Hi-Z)

state by applying a HIGH on the OE pin. The output

level is referenced to the supply voltage (VCC) and

supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2V input to 1.8V output or 1.8V input

to 3.3V output). In addition, the 5V tolerant input pins

enable down translation (for example, 3.3V to 2.5V

output).