SN74LV595A-EP中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? Qualified for automotive applications

? Available in wettable flank QFN (WBQB) package

? Customer-Specific Configuration Control Can Be

Supported Along With Major-Change Approval

? 2-V to 5.5-V VCC Operation

? Typical VOLP (Output Ground Bounce) < 0.8 V at

VCC = 3.3 V, TA = 25°C

? Typical VOHV (Output VOH Undershoot) > 2.3 V at

VCC = 3.3 V, TA = 25°C

? Supports Mixed-Mode Voltage Operation on All

Ports

? 8-Bit Serial-In, Parallel-Out Shift

? Ioff Supports Partial-Power-Down Mode Operation

? Shift Register Has Direct Clear

2 Applications

? Output expansion

? LED matrix control

? 7-segment display control

3 Description

The SN74LV595A-Q1 contains an 8-bit serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. The storage register has parallel 3-

state outputs. Separate clocks are provided for both

the shift and storage register. The shift register has

a direct overriding clear (SRCLR) input, serial (SER)

input, and a serial output for cascading. When the

output-enable (OE) input is high, all outputs except

QH' are in the high-impedance state.

The device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables

the outputs, preventing damaging current backflow

through the device when it is powered down.