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SN74LV6T14PWREP中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠(chǎng)商型號(hào) |
SN74LV6T14PWREP |
功能描述 | SN74LV6T14-EP Hex Schmitt-Trigger Inverters With Integrated Translation |
絲印標(biāo)識(shí) | |
封裝外殼 | TSSOP |
文件大小 |
1.00476 Mbytes |
頁(yè)面數(shù)量 |
24 頁(yè) |
生產(chǎn)廠(chǎng)商 | Texas Instruments |
企業(yè)簡(jiǎn)稱(chēng) |
TI1【德州儀器】 |
中文名稱(chēng) | 德州儀器官網(wǎng) |
原廠(chǎng)標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-1-20 17:08:00 |
SN74LV6T14PWREP規(guī)格書(shū)詳情
1 Features
? Wide operating range of 1.8V to 5.5V
? Single-supply voltage translator (refer to LVxT
Enhanced Input Voltage):
– Up translation:
? 1.2V to 1.8V
? 1.5V to 2.5V
? 1.8V to 3.3V
? 3.3V to 5.0V
– Down translation:
? 5.0V, 3.3V, 2.5V to 1.8V
? 5.0V, 3.3V to 2.5V
? 5.0V to 3.3V
? 5.5V tolerant input pins
? Supports standard pinouts
? Up to 150Mbps with 5V or 3.3V VCC
? Latch-up performance exceeds 250mA
per JESD 17
2 Applications
? Synchronize inverted clock inputs
? Debounce a switch
? Invert a digital signal
3 Description
The SN74LV6T14-EP device contains six
independent Inverter with Schmitt-trigger inputs. Each
gate performs the Boolean function Y = A in positive
logic. The output level is referenced to the supply
voltage (VCC) and supports 1.8-V, 2.5V, 3.3V, and 5V
CMOS levels.
The input is designed with a lower threshold circuit to
support up translation for lower voltage CMOS inputs
(for example, 1.2V input to 1.8V output or 1.8V input
to 3.3V output). In addition, the 5V tolerant input pins
enable down translation (for example, 3.3V to 2.5V
output).
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