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SN74LV6T17-Q1中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
SN74LV6T17-Q1 |
功能描述 | SN74LV6T17-EP Enhanced Product, Hex Schmitt-Trigger Buffer with Integrated Translation |
文件大小 |
1.00649 Mbytes |
頁(yè)面數(shù)量 |
24 頁(yè) |
生產(chǎn)廠商 | Texas Instruments(TI) |
企業(yè)簡(jiǎn)稱 |
TI1【德州儀器】 |
中文名稱 | 德州儀器 (TI)官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-19 9:34:00 |
SN74LV6T17-Q1規(guī)格書(shū)詳情
1 Features
? Wide operating range of 1.8V to 5.5V
? Single-supply voltage translator (refer to LVxT
Enhanced Input Voltage):
– Up translation:
? 1.2V to 1.8V
? 1.5V to 2.5V
? 1.8V to 3.3V
? 3.3V to 5.0V
– Down translation:
? 5.0V, 3.3V, 2.5V to 1.8V
? 5.0V, 3.3V to 2.5V
? 5.0V to 3.3V
? 5.5V tolerant input pins
? Supports standard pinouts
? Up to 150Mbps with 5V or 3.3V VCC
? Latch-up performance exceeds 250mA per JESD
17
2 Applications
? Enable or disable a digital signal
? Controlling an indicator LED
? Translation between communication modules and
system controllers
3 Description
The SN74LV6T17-EP device contains six
independent Buffers with Schmitt-trigger inputs. Each
gate performs the Boolean function Y = A in positive
logic. The output level is referenced to the supply
voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V
CMOS levels.
The input is designed with a lower threshold circuit to
support up translation for lower voltage CMOS inputs
(for example, 1.2V input to 1.8V output or 1.8V input
to 3.3V output). In addition, the 5V tolerant input pins
enable down translation (for example, 3.3V to 2.5V
output).
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詢價(jià) |