SST39SF512-70-4I-NHE中文資料SST數(shù)據(jù)手冊PDF規(guī)格書

PRODUCT DESCRIPTION

The SST39SF512 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF512 devices write (Program or Erase) with a 4.5-5.5V power supply. The SST39SF512 device conforms to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39SF512 devices provide a maximum Byte-Program time of 30 μsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39SF512 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

FEATURES:

? Organized as 64K x8

? Single 4.5-5.5V Read and Write Operations

? Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

? Low Power Consumption

(typical values at 14 MHz)

– Active Current: 10 mA (typical)

– Standby Current: 10 μA (typical)

? Sector-Erase Capability

– Uniform 4 KByte sectors

? Fast Read Access Time:

– 70 ns

? Latched Address and Data

? Fast Erase and Byte-Program

– Sector-Erase Time: 7 ms (typical)

– Chip-Erase Time: 15 ms (typical)

– Byte-Program Time: 20 μs (typical)

– Chip Rewrite Time: 2 seconds (typical)

? Automatic Write Timing

– Internal VPP Generation

? End-of-Write Detection

– Toggle Bit

– Data# Polling

? TTL I/O Compatibility

? JEDEC Standard

– Flash EEPROM Pinouts and command sets

? Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP