SSTEAKG8中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Pinout optimizes DDR3 RDIMM PCB layout

? DDR3-800/1066/1333/1600/1866/2133 rate

? 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs

? Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs

? Supports LVCMOS switching levels on the RESET and MIRROR inputs

? Checks priority on DIMM-independent data inputs

? Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations

and MRS command pass-through

? Supports CKE Power Down operation modes

? Supports Quad Chip Select operation features

? RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn

? Provides access to internal control words for configuring the device features and adapting in different RDIMM and system

applications

? Latch-up performance exceeds 100mA

? ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)

? Available in 176 Ball Grid Array package