ST486中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

PRODUCT OVERVIEW

The ST 486 DX core is based on the design of the SGS-THOMSON standard 486 DX4 product. The core is capable of operating at the “external” bus speed or at two or three times the bus speed up to a maximum of 120MHz. Since the design is fully static the core can operate at any frequency between D.C and 120MHz.

■ Fully Static 486 compatible core able to operate from D.C to 120MHz

■ Manufactured in a 0.35 micron five layer metal HCMOS process

■ 8K byte unified instruction and data cache with write back capability

■ Parallel processing integral floating point unit, with automatic power down mode

■ Low Power system management modes

■ Cell libraries for 2.2V and 3.3V supply with 5 V I/O interface capability

■ 2 - input NAND delay of 0.160 ns (typ) with fanout = 2.

■ Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS.

■ High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike suppression and impedance matching.

■ Generators to support SPRAM, DPRAM, ROM and many other embedded functions.

■ Fully independent power and ground configurations for inputs, core and outputs.

■ Programmable I/O ring capability up to 1000 pads.

■ Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels.

■ Active pull up and pull down devices.

■ Buskeeper I/O functions.

■ Oscillators for wide frequency spectrum.

■ Broad range of 400 SSI cells.

■ Design For Test includes LSSD macro library option and IEEE 1149.1 JTAG Boundary Scan architecture built in.

■ Cadence based design system with interfaces from multiple workstations.

■ Broad ceramic and plastic package range.

■ Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts.