STFLWARP11PL中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

GENERAL DESCRIPTION

W.A.R.P. is a VLSI Fuzzy Logic controller whose architecture arises from the need of realizing an integrated structure with high inferencing performances and flexibility. To get those results a modular architecture based on a set of parallel memory blocks has been implemented.

In orderto obtainhigh performances W.A.R.P.uses different data representations during the various phases of the computational cycle, so that it is always operating on the optimal data representation. A vectorial characterization has been adopted for the Antecedent Membership Functions. W.A.R.P. exploits a SGS-THOMSON patented strategy to store the Antecedent Membership

■ High Speed Rules Processing

■ Antecedent Membership Functions with any Shape

■ Up to 256 Rules (4 Antecedents,1 Consequent)

■ Up to 16 Input Configurable Variables

■ Up to 16 Membership Functions for an Input Variable

■ Up to 16 OutputVariables

■ Up to 128 Membership Functions for all Consequents

■ MAX-DOT Inference Method

■ Defuzzification on chip

■ Software Tools and Emulators Availability

■ 100-pin CPGA100 Ceramic Package

■ 84-lead Plastic Leaded Chip Carrier package