STGAP2SICS中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? High voltage rail up to 1200 V

? Driver current capability: 4 A sink/source @25°C

? dV/dt transient immunity ±100 V/ns in full temperature range

? Overall input-output propagation delay: 75 ns

? Separate sink and source option for easy gate driving configuration

? 4 A Miller CLAMP dedicated pin option

? UVLO function

? Gate driving voltage up to 26 V

? 3.3 V, 5 V TTL/CMOS inputs with hysteresis

? Temperature shut-down protection

? Standby function

? 6 kV galvanic isolation

? Wide body SO-8W package

? UL 1577 recognized

Description

The STGAP2SICS is a single gate driver which provides galvanic isolation between

the gate driving channel and the low voltage control and interface circuitry.

The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the

device also suitable for mid and high power applications such as power conversion

and motor driver inverters in industrial applications. The device is available in

two different configurations. The configuration with separated output pins allows

to independently optimize turn-on and turn-off by using dedicated gate resistors.

The configuration featuring single output pin and Miller CLAMP function prevents

gate spikes during fast commutations in half-bridge topologies. Both configurations

provide high flexibility and bill of material reduction for external components.

The device integrates protection functions: UVLO with optimized value for SiC

MOSFETs and thermal shut down are included to facilitate the design of highly

reliable systems. Dual input pins allow the selection of signal polarity control and

implementation of HW interlocking protection to avoid cross-conduction in case of

controller malfunction. The input to output propagation delay is less than 75 ns, which

delivers high PWM control accuracy. A standby mode is available to reduce idle

power consumption.