STLVD111BFR集成電路（IC）的時鐘緩沖器驅(qū)動器規(guī)格書PDF中文資料

STLVD111BFR屬于集成電路（IC）的時鐘緩沖器驅(qū)動器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的STLVD111BFR時鐘緩沖器，驅(qū)動器時鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負(fù)載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。

Description

The STLVD111 is a low skew programmable 1 to 10 differential LVDS driver, designed for clock distribution. The select signal is fanned out to 10 identical differential outputs.

The STLVD111 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input.

The STLVD111 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device.

The STLVD111 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can take advantage of the device’s performance to distribute low skew clocks across the backplane or the board.

Features

■ 100ps part-to part skew

■ 50ps bank skew

■ Differential design

■ Meets LVDS spec. for driver outputs and receiver inputs

■ Reference voltage available output VBB

■ Low voltage VCC range of 2.375V to 2.625V

■ High signalling rate capability (exceeds 622MHz)

■ Support open, short and terminated input fail safe (low output state)

■ Programmable drivers power off control