STM32F103TBH7TR中文資料意法半導體數(shù)據(jù)手冊PDF規(guī)格書

Features

? Arm? 32-bit Cortex?-M3 CPU core

– 72 MHz maximum frequency,?

1.25 DMIPS / MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

? Memories

– 64 or 128 Kbytes of Flash memory

– 20 Kbytes of SRAM

? Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4 to 16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

? Low-power

– Sleep, Stop and Standby modes

– VBAT supply for RTC and backup registers

? 2x 12-bit, 1 μs A/D converters (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Dual-sample and hold capability

– Temperature sensor

? DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

I2Cs and USARTs

? Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

? Debug mode

– Serial wire debug (SWD) and JTAG

interfaces

? Seven timers

– Three 16-bit timers, each with up to

4 IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– 16-bit, motor control PWM timer with ?

dead-time generation and emergency stop

– Two watchdog timers (independent and

window)

– SysTick timer 24-bit downcounter

? Up to nine communication interfaces

– Up to two I2C interfaces (SMBus/PMBus?)

– Up to three USARTs (ISO 7816 interface,

LIN, IrDA capability, modem control)

– Up to two SPIs (18 Mbit/s)

– CAN interface (2.0B Active)

– USB 2.0 full-speed interface

? CRC calculation unit, 96-bit unique ID

? Packages are ECOPACK?