STM32H725ZEH3TR中文資料意法半導體數(shù)據(jù)手冊PDF規(guī)格書

Features

Core

? 32-bit Arm? Cortex?-M7 CPU with DP-FPU, L1

cache: 32-Kbyte data cache and 32-Kbyte

instruction cache allowing 0-wait state

execution from embedded Flash memory and

external memories, frequency up to 550 MHz,

MPU, 1177 DMIPS/2.14 DMIPS/MHz

(Dhrystone 2.1), and DSP instructions

Memories

? Up to 1 Mbyte of embedded Flash memory with

ECC

? SRAM: total 564 Kbytes all with ECC, including

128 Kbytes of data TCM RAM for critical realtime

data + 432 Kbytes of system RAM (up to

256 Kbytes can remap on instruction TCM

RAM for critical real time instructions) +

4 Kbytes of backup SRAM (available in the

lowest-power modes)

? Flexible external memory controller with up to

24-bit data bus: SRAM, PSRAM,

SDRAM/LPSDR SDRAM, NOR/NAND

memories

? 2 x Octo-SPI interface with XiP

? 2 x SD/SDIO/MMC interface

? Bootloader

Graphics

? Chrom-ART Accelerator graphical hardware

accelerator enabling enhanced graphical user

interface to reduce CPU load

? LCD-TFT controller supporting up to XGA

resolution

Clock, reset and supply management

? 1.62 V to 3.6 V application supply and I/O

? POR, PDR, PVD and BOR

? Dedicated USB power

? Embedded DCDC and LDO regulator

(*)VFQFPN68 variant is DCDC only

? Internal oscillators: 64 MHz HSI, 48 MHz

HSI48, 4 MHz CSI, 32 kHz LSI

? External oscillators: 4-50 MHz HSE,

32.768 kHz LSE

Low power

? Sleep, Stop and Standby modes

? VBAT supply for RTC, 32×32-bit backup

registers

Analog

? 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to

22 channels and 7.2 MSPS in doubleinterleaved

mode