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STM32U595RJT3QTR中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書
廠商型號 |
STM32U595RJT3QTR |
功能描述 | Ultra-low-power Arm? Cortex?-M33 32-bit MCUTrustZone?FPU,240 DMIPS, up to 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI?DSI |
文件大小 |
6.98609 Mbytes |
頁面數(shù)量 |
377 頁 |
生產(chǎn)廠商 | STMicroelectronics |
企業(yè)簡稱 |
STMICROELECTRONICS【意法半導(dǎo)體】 |
中文名稱 | 意法半導(dǎo)體(ST)集團(tuán)官網(wǎng) |
原廠標(biāo)識 | |
數(shù)據(jù)手冊 | |
更新時間 | 2024-11-17 17:22:00 |
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Features
Includes ST state-of-the-art patented
technology
Ultra-low-power with FlexPowerControl
? 1.71 V to 3.6 V power supply
? - 40 °C to + 85/125 °C temperature range
? Low-power background autonomous mode
(LPBAM): autonomous peripherals with DMA,
functional down to Stop 2 mode
? VBAT mode: supply for RTC, 32 x 32-bit backup
registers and 2-Kbyte backup SRAM
? 150 nA Shutdown mode (24 wake-up pins)
? 195 nA Standby mode (24 wake-up pins)
? 480 nA Standby mode with RTC
? 2 μA Stop 3 mode with 40-Kbyte SRAM
? 8.2 μA Stop 3 mode with 2.5-Mbyte SRAM
? 4.65 μA Stop 2 mode with 40-Kbyte SRAM
? 17.5 μA Stop 2 mode with 2.5-Mbyte SRAM
? 18.5 μA/MHz Run mode at 3.3 V
Core
? Arm? 32-bit Cortex?-M33 CPU with
TrustZone?, MPU, DSP, and FPU
ART Accelerator
? 32-Kbyte ICACHE allowing 0-wait-state
execution from Flash and external memories:
frequency up to 160 MHz, 240 DMIPS
? 16-Kbyte DCACHE1 for external memories
Power management
? Embedded regulator (LDO) and SMPS
step-down converter supporting switch
on-the-fly and voltage scaling
Benchmarks
? 1.5 DMIPS/MHz (Drystone 2.1)
? 651 CoreMark? (4.07 CoreMark?/MHz)
? 369 ULPMark?-CP
? 89 ULPMark?-PP
? 47.2 ULPMark?-CM
? 120000 SecureMark?-TLS
Memories
? Up to 4-Mbyte Flash memory with ECC, 2
banks read-while-write, including 512 Kbytes
with 100 kcycles
? With SRAM3 ECC off: 2514-Kbyte RAM
including 66 Kbytes with ECC
? With SRAM3 ECC on: 2450-Kbyte RAM
including 322 Kbytes with ECC
? External memory interface supporting SRAM,
PSRAM, NOR, NAND, and FRAM memories
? 2 Octo-SPI memory interfaces
? 16-bit HSPI memory interface up to 160 MHz
Rich graphic features
? Neo-Chrom GPU (GPU2D) accelerating any
angle rotation, scaling, and perspective correct
texture mapping
? 16-Kbyte DCACHE2
? Chrom-ART accelerator (DMA2D) for smooth
motion and transparency effects
? Chrom-GRC (GFXMMU) allowing up to 20
of graphic resources optimization
? MIPI? DSI Host controller with two DSI lanes
running at up to 500 Mbit/s each
? LCD-TFT controller (LTDC)
? Digital camera interface
General-purpose input/outputs
? Up to 156 fast I/Os with interrupt capability
most 5V-tolerant and up to 14 I/Os with
independent supply down to 1.08 V
Clock management
? 4 to 50 MHz crystal oscillator
? 32 kHz crystal oscillator for RTC (LSE)
? Internal 16 MHz factory-trimmed RC (± 1 )
? Internal low-power 32 kHz RC (± 5 )
? 2 internal multispeed 100 kHz to 48 MHz
oscillators, including one auto-trimmed by LSE
(better than ±0.25 accuracy)
? Internal 48 MHz
? 5 PLLs for system clock, USB, audio, ADC, DSI
Security
? Arm? TrustZone? and securable I/Os,
memories, and peripherals
? Flexible life-cycle scheme with RDP and
password-protected debug
? Root of trust thanks to unique boot entry and
secure hide-protection area (HDP)
? Secure firmware installation (SFI) thanks to
embedded root secure services (RSS)
? Secure firmware upgrade support with TF-M
? HASH hardware accelerator
? True random number generator, NIST
SP800-90B compliant
? 96-bit unique ID
? 512-byte OTP (one-time programmable)
? Active tampers
Up to 17 timers, 2 watchdogs and RTC
? 19 timers: 2 16-bit advanced motor-control,
4 32-bit, 3 16-bit general purpose, 2 16-bit
basic, 4 low-power 16-bit (available in Stop
mode), 2 SysTick timers, and 2 watchdogs
? RTC with hardware calendar, alarms, and
calibration
Up to 25 communication peripherals
? 1 USB Type-C?/USB power delivery controller
? 1 USB OTG high-speed with embedded PHY
? 2 SAIs (serial-audio interface)
? 6 I2C FM+(1 Mbit/s), SMBus/PMBus?
? 7 USARTs (ISO 7816, LIN, IrDA, modem)
? 3 SPIs (6x SPIs with OCTOSPI/HSPI)
? 1 CAN FD controller
? 2 SDMMC interfaces
? 1 multi-function digital filter (6 filters) + 1 audio
digital filter with sound-activity detection
? Parallel synchronous slave interface
Mathematical coprocessor
? CORDIC for trigonometric functions
acceleration
? FMAC (filter mathematical accelerator)
Rich analog peripherals (independent
supply)
? 2 14-bit ADC 2.5-Msps with hardware
oversampling
? 1 12-bit ADC 2.5-Msps, with hardware
oversampling, autonomous in Stop 2 mode
? 12-bit DAC (2 channels), low-power sample,
and hold, autonomous in Stop 2 mode
? 2 operational amplifiers with built-in PGA
? 2 ultra-low-power comparators