SY100E195JCTR中文資料麥瑞半導體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition.

The delay section consists of a chain of gates organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E195 with a digitally-selectable resolution of approximately 20ps.

FEATURES

■ Up to 2ns delay range

■ Extended 100E VEE range of –4.2V to –5.5V

■ ≈20ps/digital step resolution

■ >1GHz bandwidth

■ On-chip cascade circuitry

■ 75Kk? input pulldown resistor

■ Fully compatible with Motorola MC10E/100E195

■ Available in 28-pin PLCC package