SY100EL15ZCTR中文資料麥瑞半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to VCC via a 0.01μF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.

FEATURES

■ 50ps output-to-output skew

■ Synchronous enable/disable

■ Multiplexed clock input

■ 75K? internal input pull-down resistors

■ Available in 16-pin SOIC package