首頁>SY100EL34ZGTR>規(guī)格書詳情
SY100EL34ZGTR中文資料麥瑞半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

廠商型號 |
SY100EL34ZGTR |
功能描述 | 5V/3.3V ?2, ?4, ?8 Clock Generation Chip |
文件大小 |
176.55 Kbytes |
頁面數(shù)量 |
7 頁 |
生產(chǎn)廠商 | Micrel Semiconductor |
企業(yè)簡稱 |
Micrel【麥瑞半導(dǎo)體】 |
中文名稱 | 麥瑞半導(dǎo)體官網(wǎng) |
原廠標(biāo)識 | ![]() |
數(shù)據(jù)手冊 | |
更新時(shí)間 | 2025-5-4 11:10:00 |
人工找貨 | SY100EL34ZGTR價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
SY100EL34ZGTR規(guī)格書詳情
General Description
The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low-skew clock generation applications. The internal dividers are synchronous to each other; therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01μF capacitor. The VBB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.
The common enable (EN ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system.
Features
? 3.3V and 5V power supply options
? 50ps output-to-output skew
? Synchronous enable/disable
? Master Reset for synchronization
? Internal 75K? input pull-down resistors
? Available in 16-pin SOIC package
產(chǎn)品屬性
- 型號:
SY100EL34ZGTR
- 制造商:
MICREL
- 制造商全稱:
Micrel Semiconductor
- 功能描述:
5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
MIC |
23+ |
SOP-8 |
11200 |
原廠授權(quán)一級代理、全球訂貨優(yōu)勢渠道、可提供一站式BO |
詢價(jià) | ||
MICREL |
25+ |
SOIC-16L |
2500 |
強(qiáng)調(diào)現(xiàn)貨,隨時(shí)查詢! |
詢價(jià) | ||
MICREL/麥瑞 |
23+ |
SOP16 |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
Micrel |
24+ |
16SOIC |
28500 |
授權(quán)代理直銷,原廠原裝現(xiàn)貨,假一罰十,特價(jià)銷售 |
詢價(jià) | ||
MICREL |
20+ |
SOP16 |
1128 |
進(jìn)口原裝現(xiàn)貨,假一賠十 |
詢價(jià) | ||
Microchip |
22+ |
16SOIC |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
Microchip Technology |
24+ |
16-SOIC |
56200 |
一級代理/放心采購 |
詢價(jià) | ||
MICREL/麥瑞 |
0448+ |
SOIC-16L |
1000 |
原裝現(xiàn)貨 |
詢價(jià) | ||
MICREL |
24+ |
SOIC-16L |
15300 |
公司常備大量原裝現(xiàn)貨,可開13%增票! |
詢價(jià) | ||
MICREL/麥瑞 |
2405+ |
原廠封裝 |
12500 |
15年芯片行業(yè)經(jīng)驗(yàn)/只供原裝正品:0755-83267371鄒小姐 |
詢價(jià) |