首頁(yè)>SY100S351JCTR>規(guī)格書詳情
SY100S351JCTR中文資料麥瑞半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書
SY100S351JCTR規(guī)格書詳情
DESCRIPTION
The SY100S351 offers six D-type, edge-triggered, master/slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals (CPa, CPb). Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb (or both) go to a logic HIGH. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75K? pull-down resistors.
FEATURES
■ Max. toggle frequency of 700MHz
■ Clock to Q max. of 1200ps
■ IEE min. of –98mA
■ Industry standard 100K ECL levels
■ Extended supply voltage option: VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved noise immunity
■ Internal 75K? input pull-down resistors
■ 50 faster than Fairchild 300K
■ Better than 20 lower power than Fairchild
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC packages
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
SYNERGY |
23+ |
DIP24 |
28533 |
原盒原標(biāo),正品現(xiàn)貨 誠(chéng)信經(jīng)營(yíng) 價(jià)格美麗 假一罰十! |
詢價(jià) | ||
SYNERGY |
2016+ |
CDIP24P |
6523 |
只做原裝正品現(xiàn)貨!或訂貨! |
詢價(jià) | ||
SYNERGY |
23+ |
DIP/24/磁 |
7000 |
絕對(duì)全新原裝!100%保質(zhì)量特價(jià)!請(qǐng)放心訂購(gòu)! |
詢價(jià) | ||
Micrel |
23+ |
28-PLCC |
7750 |
全新原裝優(yōu)勢(shì) |
詢價(jià) | ||
SYNERGY |
QFP |
699839 |
集團(tuán)化配單-有更多數(shù)量-免費(fèi)送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢價(jià) | |||
Microchip Technology |
24+ |
28-LCC(J 形引線) |
56300 |
一級(jí)代理/放心采購(gòu) |
詢價(jià) | ||
SYNERGY |
23+ |
IC |
66600 |
專業(yè)芯片配單原裝正品假一罰十 |
詢價(jià) | ||
MICREL |
2024+ |
SOP |
50000 |
原裝現(xiàn)貨 |
詢價(jià) | ||
Microchip |
23+ |
28LCC (JLead) |
8000 |
只做原裝現(xiàn)貨 |
詢價(jià) | ||
微芯 |
22+ |
NA |
500000 |
萬(wàn)三科技,秉承原裝,購(gòu)芯無(wú)憂 |
詢價(jià) |
