SY100S863JCTR中文資料麥瑞半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The SY100S863 is a PECL 8:1 multiplexer designed for use in new, high-performance PECL systems. It has differential PECL outputs and a standard TTL output. The TTL select inputs (SEL0, SEL1, SEL2) determine which one of the eight differential PECL data inputs (D0–D7) is propagated to the outputs. The enable pin, EN, is provided for expansion. When EN is at a TTL logic one level, both PECL and TTL outputs are enabled. When the enable pin is set to TTL logic zero level, both PECL outputs of the differential pair are in cut-off and the TTL output is in a three-state condition.

FEATURES

■ Low skew

■ Differential PECL inputs

■ Differential cut-off PECL outputs capable of driving 25? load for driving data bus

■ Tri-state TTL output

■ TTL select and enable input

■ Internal 75K? PECL input pull-down resistors

■ PECL I/O fully compatible with industry standard

■ Available in 28-pin PLCC package