T83C5101中文資料Temic數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

TEMIC T8xC5101/02 family is a high performance CMOS ROM, OTP, EPROM derivative of the 80C51 CMOS single chip 8-bit microcontroller.

Features

● 80C51 code Compatible

? 8051 instruction compatible

? 16 I/O + 2 Outputs in 24 pin packages

16 I/O + 6 Outputs in 28 pin packages

? Three 16-bit timer/counters

? 256 bytes scratchpad RAM

● Program Memory

? 8Kb ROM T83C5102

? 16Kb ROM T83C5101

? 16Kb EPROM/OTP T87C5101

● High-Speed Architecture

? 40 MHz from 2.7 to 5.5V, commercial or industrial temperature range :

- 40 MHz with a 40 MHz crystal in std mode

- 40 MHz with a 20 MHz crystal in X2 mode

? 66 MHz from 4.5 to 5.5V, commercial temperature range

- 40MHz with a 40 MHz crystal in std mode

- 66MHz with a 33MHz crystal in X2 mode

● Dual Data Pointer

● On-chip eXpanded RAM (XRAM) (256 bytes)

● Programmable Clock Out and Up/Down Timer/ Counter 2

● Asynchronous port reset

● Interrupt Structure with

? 6 Interrupt sources,

? 4 level priority interrupt system

● Full duplex Enhanced UART

? Framing error detection

? Automatic address recognition

● Low EMI (no ALE)

● Power Control modes

? Idle mode

? Power-down mode

● Packages: SO24, DIL24, TSSOP24*, SO28*

* check for availability