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Application Information

The TCP862 is a standard 3U 32 bit CompactPCI module with four high speed serial data communication channels.

The TCP862-10 provides front panel I/O via HD68 SCSI-3 type connector and TCP862-20 additionally provides rear I/O via J2.

An Infineon PEF 20534 DMA Supported Serial Communication Controller (DSCC4) with integrated bus master PCI interface is used.

Several interrupt sources can generate interrupts on INTA for each channel. Interrupts can be enabled and disabled separately.

A 14.7456 MHz oscillator provides standard asynchronous baud rates. An additional 24 MHz oscillator is provided for other baud rates. A 10 MHz oscillator is used for the maximum synchronous baud rate of 10 Mbit/s.

Each channel can support many serial communication protocols such as HDLC, SDLC, PPP, asynchronous, monosynchronous, bisynchronous.

Multiprotocol transceivers are used for the line interface. The physical interface can be selected by software individually for each channel as EIA-232, EIA-422, EIA-449, EIA-530, EIA-530A, V.35, V.36 or X.21.

The TCP862 supports Receive Data (RxD +/-), Transmit Data (TxD +/-), Receive Clock (RxC +/-), Transmit Clock (TxC +/-), Ready-To-Send (RTS +/-), Clear-To-Send (CTS +/-), Carrier-Detect (CD +/-) and GND for each channel. Additionally serial channel three provides Data-Set-Ready (DSR3 +/-) and Data-Terminal-Ready (DTR3 +/-), both over front I/O only.

The local control logic provides additional features, e.g. multiplexing and inverting clock signals and supporting all clock modes of the DSCC4 conveniently.

The device contains a central receive and transmit FIFO of 128 long words (32 bit) each. Furthermore each channel has a 17 long words deep receive FIFO and an 8 long words deep transmit FIFO.

For First Time Users the Engineering Documentation TCP862-ED is recommended. The Engineering Documentation includes TCP862-DOC, schematics and data sheets.

Driver support (TDRV001-SW-xx) for different operating systems is available.