TA304中文資料TEWS數(shù)據(jù)手冊PDF規(guī)格書

Application Information

The TPCE863 is a standard height, half-length PCI

Express 1.1 compliant module with four high speed serial

data communication channels.

The serial communication controller is implemented in

FPGA logic, along with a bus master capable PCI

interface, guaranteeing long term availability with the

option to implement additional functions in the future. The

FPGA is connected to the PCI Express interface via a

transparent PCI Express to PCI bridge.

Each channel has a receive and a transmit FIFO of 512

long words (32 bit) per channel for high data throughput.

Data transfer on the PCI Express bus is handled via

TPCE863 initiated DMA cycles with minimum host/CPU

intervention.

Several serial communication protocols are supported by

each channel, such as asynchronous, isochronous,

synchronous and HDLC mode.

A 14.7456 MHz oscillator provides standard asynchronous

baud rates. A 24 MHz and a 10 MHz oscillator are

provided for other (synchronous) baud rates.

Additionally each channel provides various interrupt

sources, generated on INTA. The interrupt sources can be

enabled or disabled individually.

Multiprotocol transceivers are used for the line interface.

The physical interface is selectable by software,

individually for each channel as EIA-232, EIA-422,

EIA-449, EIA-530, EIA-530A, V.35, V.36 or X.21.

A HD68 SCSI-3 type connector at the front panel provides

access to the I/O lines.

The following signals are provided by the TPCE863 for

each channel at the front I/O connector:

Receive Data (RxD +/-), Transmit Data (TxD +/-), Receive

Clock (RxC +/-), Transmit Clock (TxC +/-), Ready-To-Send

(RTS +/-), Clear-To-Send (CTS +/-), Carrier-Detect

(CD +/-) and GND. Additionally, serial channel 3 provides

Data-Set-Ready (DSR3 +/-) and Data-Terminal-Ready

(DTR3 +/-).

A serial EEPROM is used to store detailed board

information and special configuration parameters.