General

Toshiba CMOS Gate Array family, TC11 OG Series,

with interconnect routing which is not confined to

routing channels. This technique increases silicon

efficiency (functions/mm2

).

Higher density and Toshiba HC2MOS process

provide subnanosecond speeds of 0.6ns typical gate

delays (2-input NAND gate, fanout=2, tpd.). TC110G

Series is introduced as 14 base arrays with 1 .4K to

50K estimated usable gates.

Gate Array design using TC 11 OG Series is supported

by the TOSHIBA MAINFRAME CAD SYSTEM.

Hierarchical designs with large macro capabilites

Features

Proprietary 1.5μm HC2MOS/VLSI process technology.

?0.6ns speed (2-input NAND gate, fanout = 2, tpd.)

Achieves ultra high speed equivalent to 10K ECL.

High packing density up to 129K raw gates.

3K to 129K raw gates.

Up to 256 110 pins.

Variable channel width architecture allows efficient silicon utilization.

Full input/output TTL/CMOS compatibility.

Advanced packaging techniques.

Design is fully supported by TOSHIBA MAINFRAME CAD SYSTEM

Programmable I/O cells with siew rate control (e.g. Output drive up to 12mA).

Large macro capability (e.g. RAMs, ROMs, Megafunctions, Megacells* ).

Performance optimization (e.g. Standard/High drive cells).