TC358764XBG中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

● DSI Receiver

? Configurable 1- up to 4-Data-Lane DSI Link with

bi-directional support on Data Lane 0

? Maximum bit rate of 800 Mbps/lane

? Video input data formats:

- RGB565 16 bits per pixel

- RGB666 18 bits per pixel

- RGB666 loosely packed 24 bits per pixel

- RGB888 24 bits per pixel.

? Video frame size:

- Up to 1366×768 24-bit/pixel resolution to

single-link LVDS display panel

- Up to WUXGA resolutions (1920×1200 18-bit

pixels) to dual-link LVDS display panel

? Supports Video Stream packets for video data

transmission.

? Supports generic long packets for accessing the

chip’s register set

? Supports the path for Host to control the on-chip I2C

Master

● LVDS FPD Link Transmitter

? Supports single-link or dual-link

? Maximum pixel clock frequency of 85 MHz

? Maximum throughput of 297.5 MBytes/sec for

single-link or 595 Mbytes/sec for dual-link

? Supports display up to 1366×768 24-bit/pixel

resolution for single-link, or up to WUXGA (18

bit/pixel) resolutions for dual-link

? Supports the following pixel formats:

- RGB666 18 bits per pixel

- RGB888 24 bits per pixel

? Flexible mapping of parallel data input bit ordering

? Supports power-down

● System Operation

? Host configures the chip through DSI link

? Through DSI link, Host accesses the chip register set

using Generic Write and Read packets. One Generic

Long Write packet can write to multiple contiguous

register addresses

? Includes an I2C Master function which is controlled

by Host through DSI link (multi-master is not

supported)

? Power management features to save power

? Configuration registers is also accessible through

I2C Slave interface

● Clock Source

? LVDS pixel clock source is either from external

clock EXTCLK or derived from DSICLK.

? A built-in PLL generates the high-speed LVDS

serializing clock requiring no external components

● Digital Input/Output Signals

? All Digital Input signals are 3.3V tolerant

? All Digital Output signals can output ranging from

1.8V to 3.3V depending on IO supply voltage

● Power supply

? MIPI? DSI D-PHY: 1.2 V

? LVDS PHY: 3.3 V

? I/O: 1.8 V - 3.3V (all IO supply pins must

be same level)

? Digital Core: 1.2 V

● Power Consumption

? Power –down mode is achieved by:

1. Disable PLL (0x04A0[8] = 1) and LVDS

(0x049C[0] = 0) after stopping video stream (in

DSI LP11 state)

2. Drive DSI Data Lanes to LP00 state

3. Stop DSIClk and/or RefClk

? Power-down mode : Power Consumption: to 55 μW

- DSI-RX: 10.39 μA

- LVDS_1.2V: 3.10 μA

- LVDS_3.3V: 0.015 μA

- CORE: 31.96 μA

- IOs_1.8V: 0.15 μA

? Normal Operation (2-DSI Data lane @ 200 MHz,

Single LVDS @ 27 MHz): to 157.58 mW

- DSI-RX 2 lanes 8.25 mA

- LVDS_3.3V: 42.68 mA

- LVDS_1.2V: 1.25 mA

- CORE 4.34 mA

- IOs_1.8V 0.067 mA

? Normal Operation (2-DSI Data lane @ 314 MHz,

Dual LVDS @ 44.25 MHz each): to 259.16 mW

- DSI-RX 2 lanes: 9.77 mA

- LVDS_3.3V: 69.63 mA

- LVDS_1.2V: 7.78 mA

- CORE: 6.83 mA

- IOs_1.8V: 0.061 mA

● Packaging Information

? TC358765XBG : BGA64 (0.65mm ball pitch)

- Supports DSI-RX 4-data-lanes + Dual-Link

LVDS-TX

- 6.0mm × 6.0mm × 1.2mm

? TC358764XBG : BGA49 (0.65mm ball pitch)

- Supports DSI-RX 4-data-lanes + Single-Link

LVDS-TX

- 5.0mm × 5.0mm × 1.2mm