TC518129CFTL-70中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The TC518129CPL/CFL/CFWL/CFTL is a 1,048,578-bit CMOS pseudo static random access memory (PSRAM)

organized as 131,072 words by 8 bits. It feature a one-transistor dynamic memory cell using CMOS peripheral

circuitry to provide large capacity, high speed and low power. It uses a single 5 V ± 10 power supply. A

RFSH input selects either auto or self refresh operation. This device family also features SRAM-like write

functions whereby data is written to the memory cell rising edge of R/W signal, for easy interfacing to

microprocessors. The CE2 pin of the TC518128C family is replaced by the CS pin in this device family for

standby mode operation. The TC518129CPL/CFL/CFWL/CFTL is available in molded 32-pin standard 0.6-

inch dual-inline plastic packages (DIP) and 0.525-inch small-outline plastic packages (SOP), and thin small-

outline plastic package (TSOP).

FEATURES

Organized

(1,048,576

as 131,072 words by 8 bits

bits).

Fast access time and low power dissipation.

? Single power supply voltage of 5 V ± 10.

TC518129C Family

tCEA CE Access Time

TOFA OE Access Time

tec Cycle Time

Power Dissipation

Self Refresh Current

-70

70 ns

25 ns

115 ns

385 mW

-80

-10

100 ns

40 ns

160 ns

80 ns

30 ns

130 ns

330 mW | 275 mW

100A (L version)

50 μA (LL version)

Internal counter can be used for auto and self refresh

operations.

Internal timer can be used for self refresh operation.

Auto refresh power down function.

512 refresh cycles per 8 ms.

All inputs and outputs are TTL compatible.

● Pin compatible with 1M SRAM (JEDEC).

Logic compatible with SRAM R/W pin.

Packages:

DIP32-P-600-2.54

SOP32-P-525-1.27

(CPL)

(CFWL)

(Weight: 4.45 g typ)

(Weight: 1.04 g typ)

TSOP I 32-P-0820-0.50 (CFTL) (Weight: 0.32 g typ)